The present invention relates to semiconductor integrated circuits containing memory arrays, and particularly those arrays incorporating array lines having extremely small pitch, and more particularly those having a three-dimensional memory array.
Semiconductor integrated circuits have progressively reduced their feature linewidths into the deep sub-micron regime. Moreover, recent developments in certain memory cell technologies have resulted in word lines and bit line having an extremely small pitch. For example, certain passive element memory cell arrays may be fabricated having word lines approaching the minimum feature size (F) and minimum feature spacing for the particular word line interconnect layer, and also having bit lines approaching the minimum feature width and minimum feature spacing for the particular bit line interconnect layer. Moreover, three-dimensional memory arrays having more than one plane of memory cells have been fabricated implanting such so-called 4F2 memory cells on each memory plane. Exemplary three-dimensional memory arrays are described in U.S. Pat. No. 6,034,882 to Johnson, entitled “Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication.”
However, the area required for implementing decoder circuits for word lines and bit lines has not achieved such dramatic reductions. Consequently, interfacing the word line decoders and bit line decoders to such tightly spaced word lines and bit lines within such very dense arrays has become extremely difficult, and limits the density of memory arrays otherwise achievable. There remains a continued need for improved decoder structures capable of interfacing with large numbers of array lines having a very small pitch, and particularly if such array lines exist on more than one layer, as in a three-dimensional memory array having more than one plane of memory cells.